Start your career in ASIC Digital Design & Verification!!
- Final Year Students & Graduates
- B.E/B.Tech from ECE / EEE branches
- M.E/M.Tech in VLSI Stream
- B.Sc/M.Sc in Electronics & Communications Engineering
- Grade: 60% / CGPA 7.0 & above
Candidate need to sign up for online screening test through registration process.Selection Criteria
Candidate selection is subject to qualification in all India level Screening Test (Includes Online Test & Interview).
- Engineering Mathematics
- Basics of Electronics and Electrical Engineering
- Digital Electronics
- C Programming
- The fee towards training during probationary training is Rs.1,00,300 (Inclusive of GST @ 18%)
- Probationary trainees are eligible for flexi payment of probationary training fee
- 50% on enrollment
- 25% on reporting
- Final 25% within 30 days from the reporting date
- Program Duration: 6 months
- Program Starts from: December, 2018
- Venue: Bangalore
- Digital Fundamentals, ASIC Flow, EDA Tools
- Linux Environment, vi editor
- Verilog for Design(RTL) and Verification(Test Bench)
- System Verilog constructs – Classes, Interfaces etc.
- System Verilog for Verification
- System Verilog Test bench for a Design Block
- Verification Methodologies
- Driver, Sequence, Sequencer, Monitor, Scoreboard
- TLM, Agent, Env and Test
- The engineers enter as Interns
- They will be trained in Verilog, System Verilog, and UVM
- Mentored for Verification Project execution
- Acquire Protocol Knowledge – Bus/Layered
- Learn Test bench automation – scripting
- Exposed to Configuration Management system
- Learn to carryout Block Verification Independently
- Acquire work experience in real-time projects/Verification IP development
Upon successful completion of training, qualified probationary trainees shall be offered Employment at Entuple Technologies/Sarvakarma Solutions/Goldenlight VLSI Pvt Ltd/ & their customers.
All accommodation & logistics to be taken care by candidates on their own.