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ASIC Physical Design & Verification - Course Details
ASIC Physical Design & Verification - Course Details
This training consists reinforcement of Digital fundamentals and RTL Design concepts, Immersive assignments on Scripting Extensive Hands-on sessions Physical Design and Verification, Practical Industrial Project, Case studies and Periodic assessments.
Eligibility Criteria
  • Final Year Students & Graduates
    • B.E/B.Tech from ECE / EEE branches
    • M.E/M.Tech in VLSI Stream
    • B.Sc/M.Sc in Electronics & Communications Engineering
  • Grade: 60% / CGPA 7.0 & above
Registration

Candidate need to sign up for online screening test through registration process.

Selection Criteria
Candidate selection is subject to qualification in all India level Screening Test (Includes Online Test & Interview).
Topics of evaluation:
  • Engineering Mathematics
  • Basics of Electronics and Electrical Engineering
  • Digital Electronics
  • C Programming
Course Fee
  • The fee towards training during probationary training is Rs.1,18,000 (Inclusive of GST @ 18%)
  • Probationary trainees are eligible for flexi payment of probationary training fee
    1. 50% on enrollment
    2. 25% on reporting
    3. Final 25% within 30 days from the reporting date
  • Rs.10,000 early bird discount for candidates enrolling for the program on or before 30th November 2018.
  • Training fee is non-refundable.
Probationary Program Duration & Venue
  • Program Duration: 6 months
  • Program Starts from: December, 2018
  • Venue: Bangalore
Probationary Training Details - ASIC Physical Design & Verification
This training consists reinforcement of Digital fundamentals and RTL Design concepts, Immersive assignments on Scripting Extensive Hands-on sessions Physical Design and Verification, Practical Industrial Project, Case studies and Periodic assessments.
DESIGN BASICS AND LINUX, SCRIPTING
  • VLSI Industry Overview
  • VLSI Basics and Flow
  • CMOS IC Design concepts
  • DSM Technology (CMOS, FinFET)
  • Linux and Scripting
RTL DESIGN AND SYNTHESIS
  • RTL Design using Verilog HDL
  • RTL Synthesis – synthesis flow, constraints
  • Basics of Static Timing Analysis
  • Pre-Layout Static Timing Analysis
PHYSICAL DESIGN IMPLEMENTATION
  • Physical Design and Verification flow
  • Floorplan
  • Place & Route
  • Clock Tree Synthesis
  • Post Layout Static Timing Analysis
  • Physical Verification – DRC, LVS, ERC
  • Sign-off checks and Tape out
PROJECT – PHYSICAL DESIGN AND VERIFICATION BLOCK IMPLEMENTATION
Trainee engineers will be subjected to 8-week project work that tests their overall skill on
  • Digital Fundamentals
  • RTL Design
  • Scripting
  • Logic Synthesis
  • Floor Plan
  • Place and route
  • CTS
  • STA
  • Physical Verification
  • Sign-off checklist
Internship & Placement Assurance

Trainee engineers from final year UG/PG also receive industrial training/internship certificate.

Trainees will earn project completion certificate for the work they complete during the probationary period. The same can be submitted towards final year project dissertation as per academic norms.

Upon successful completion of training, qualified probationary trainees shall be offered Employment at Entuple Technologies/Sarvakarma Solutions/Goldenlight VLSI Pvt Ltd/ & their customers.

Accommodation & Logistics

All accommodation & logistics to be taken care by candidates on their own.

Interested in VLSI..? Submit your Registration Now
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  • Registration includes online screening test fee of INR 1550 (Inclusive of all taxes)
  • Screening test fee is non refundable. Any request for refunds & cancellation will not be entertained
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