Start your career in ASIC Digital Design & Verification!!
- Final Year Students & Graduates
- B.E/B.Tech from ECE / EEE branches
- M.E/M.Tech in VLSI Stream
- B.Sc/M.Sc in Electronics & Communications Engineering
- Grade: 60% / CGPA 7.0 & above
Candidate need to sign up for online screening test through registration process.Selection Criteria
Candidate selection is subject to qualification in all India level Screening Test (Includes Online Test & Interview).
- Engineering Mathematics
- Basics of Electronics and Electrical Engineering
- Digital Electronics
- C Programming
- Program Duration: 8 months
- Program Starts from: 17th June 2019
- Venue: Bangalore
- Digital Fundamentals, ASIC Flow, EDA Tools
- Linux Environment, vi editor
- Verilog for Design(RTL) and Verification(Test Bench)
- System Verilog constructs – Classes, Interfaces etc.
- System Verilog for Verification
- System Verilog Test bench for a Design Block
- Verification Methodologies
- Driver, Sequence, Sequencer, Monitor, Scoreboard
- TLM, Agent, Env and Test
- The engineers enter as Interns
- They will be trained in Verilog, System Verilog, and UVM
- Mentored for Verification Project execution
- Acquire Protocol Knowledge – Bus/Layered
- Learn Test bench automation – scripting
- Exposed to Configuration Management system
- Learn to carryout Block Verification Independently
- Acquire work experience in real-time projects/Verification IP development
Upon successful completion of probationary training, placement assistant shall be offered by Entuple Technologies/Sarvakarma Solutions Pvt. Ltd.
All accommodation & logistics to be taken care by candidates on their own.