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ASIC Digital Design & Verification - Course Details
ASIC Digital Design & Verification - Course Details
This training reinforces Digital Electronics and Digital Design concepts. It addresses Scripting for Verification, HDL based Verification with Verilog HDL, Verification using SystemVerilog and Unified Verification Methodology (UVM), Gate Level Simulation(GLS) and Protocol Verification with extensive hands-on sessions. The trainees will be put through practical industrial project, case studies and periodic assessments.
Eligibility Criteria
  • Final Year Students & Graduates
    • B.E/B.Tech from ECE / EEE branches
    • M.E/M.Tech in VLSI Stream
    • B.Sc/M.Sc in Electronics & Communications Engineering
  • Grade: 60% / CGPA 7.0 & above
Registration

Candidate need to sign up for online screening test through registration process.

Selection Criteria
Candidate selection is subject to qualification in all India level Screening Test (Includes Online Test & Interview).
Topics of evaluation:
  • Engineering Mathematics
  • Basics of Electronics and Electrical Engineering
  • Digital Electronics
  • C Programming
Probationary Program Duration & Venue
  • Program Duration: 8 months
  • Program Starts from: 17th June 2019
  • Venue: Bangalore
Probationary Training Details - ASIC Digital Design & Verification
This training reinforces Digital Electronics and Digital Design concepts. It addresses Scripting for Verification, HDL based Verification with Verilog HDL, Verification using SystemVerilog and Unified Verification Methodology (UVM), Gate Level Simulation(GLS) and Protocol Verification with extensive hands-on sessions. The trainees will be put through practical industrial project, case studies and periodic assessments.
DIGITAL DESIGN BASICS AND VERILOG
  • Digital Fundamentals, ASIC Flow, EDA Tools
  • Linux Environment, vi editor
  • Verilog for Design(RTL) and Verification(Test Bench)
SYSTEM VERILOG
  • System Verilog constructs – Classes, Interfaces etc.
  • System Verilog for Verification
  • System Verilog Test bench for a Design Block
UNIVERSAL VERIFICATION METHODOLOGY (UVM)
  • Verification Methodologies
  • Driver, Sequence, Sequencer, Monitor, Scoreboard
  • TLM, Agent, Env and Test
PROTOCOL UNDERSTANDING-BUS, LAYERED
PROJECT – SYSTEM VERILOG UVM
VERSION CONTROL SYSTEM (CVS/SVN)
What the engineers learn in Digital Design Track?
  • The engineers enter as Interns
  • They will be trained in Verilog, System Verilog, and UVM
  • Mentored for Verification Project execution
  • Acquire Protocol Knowledge – Bus/Layered
  • Learn Test bench automation – scripting
  • Exposed to Configuration Management system
  • Learn to carryout Block Verification Independently
  • Acquire work experience in real-time projects/Verification IP development
Career Opportunities

Upon successful completion of probationary training, placement assistant shall be offered by Entuple Technologies/Sarvakarma Solutions Pvt. Ltd.

Accommodation & Logistics

All accommodation & logistics to be taken care by candidates on their own.

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